1. Field of the Invention
The present invention relates to a substrate for a display, a method of manufacturing the same and a display having the same and, more particularly, to a liquid crystal display substrate to be used for an active matrix liquid crystal display utilizing switching elements such as thin film transistors (TFTs) and a method of manufacturing the same.
The invention also relates to a liquid crystal display substrate to be used for a liquid crystal display having a protective insulation layer (insulatiing resin layer) made of an insulating organic resin material provided on an array substrate having switching elements formed thereon and a method of manufacturing the same.
Furthermore, the invention relates to a liquid crystal display substrate to be used for a reflective liquid crystal display whose pixel electrodes are formed of a light-reflecting material and a method of manufacturing the same. The invention also relates to a substrate to be used for a liquid crystal display having a CF-on-TFT structure in which resin color filter (CF) layers are formed on an array substrate and a method of manufacturing the same.
2. Description of the Related Art
For example, an active matrix liquid crystal display (LCD) utilizing TFTs as switching elements is disclosed in Patent Document 4. As schematically described below, Patent Document 4 discloses a configuration of a transmissive LCD having inverted staggered structure TFTs formed with a channel protection film.
A passivation film made of an inorganic insulating material is formed on a substantially entire surface of an array substrate having TFTs formed thereon (hereinafter referred to as “TFT substrate”). Pixel electrodes made of a transparent electrode material is formed on the passivation film. The pixel electrodes are connected to source electrodes of the TFTs through contact holes that are openings in the passivation film.
An external connection terminal connected to a drain bus line (hereinafter simply referred to as “drain terminal”) has a bottom electrode formed by an n+ a-Si layer and a metal layer which are the same layers that constitute source and drain electrodes and drain bus lines of the TFTs. A top electrode constituted by a conductive oxide film made of the same material as the pixel electrodes is stacked on the bottom electrode, a contact hole in the passivation film intervening between the electrodes. Connection terminals of a drain bus line driving circuit are connected to the top electrodes to apply a predetermined tone voltage to each drain bus line.
An external connection terminal connected to a gate bus line (hereinafter referred to as “gate terminal”) has a bottom electrode formed by a metal layer which is the same layer that constitutes gate electrodes and gate bus lines. A top electrode constituted by a conductive oxide film made of the same material as the pixel electrodes is stacked on the bottom electrode, an insulation film which is the same layer that constitutes a gate insulation film and a contact hole provided in the passivation film intervening between the electrodes. Connection terminals of a gate bus line driving circuit are connected to the top electrodes to apply a predetermined gate pulse to the gate bus lines sequentially. The top electrodes of the gate terminals and the drain terminals prevent oxidation of the bottom electrodes. This makes it possible to improve the reliability of the gate terminals and the drain terminals in the long term and to prevent connection failures at both of the terminals.
A brief description will now be made on a method of manufacturing a transmissive LCD having inverted staggered structure TFTs formed with a channel protection film. A plurality of gate bus lines and gate terminal bottom electrodes are formed on a transparent insulated substrate such as a glass substrate. Next, an insulation film is formed throughout the substrate (the film may be hereinafter referred to as “gate insulation film” depending on the position where the film is formed). Subsequently, an amorphous silicon (a-Si) layer is formed on the insulation film, and channel protection films are then formed. Next, after forming an n+ a-Si layer, a metal layer is formed. The metal layer, the n+ a-Si layer and the a-Si layer are simultaneously etched using the channel protection films as an etching stopper. Thus, active semiconductor layers constituted by a-Si layers are formed on the gate insulation film in TFT regions, and source electrodes and drain electrodes are formed on both sides of the channel protection films to complete the TFTs. At the same time when the source electrodes and the drain electrodes are formed, drain bus lines and drain terminal bottom electrodes connected to the drain bus lines are formed.
A passivation film having a thickness of 400 nm constituted by a silicon nitride film (SiN film) or a silicon oxide film (SiO2 film) which is an inorganic insulating material or a combination of those films is formed throughout the substrate. A resist is then applied, and a photolithographic process is thereafter used to form a resist pattern having an opening above each of the source electrodes, drain terminal bottom electrodes and the gate terminal bottom electrodes. The passivation film or the combination of the passivation film and the insulation film is etched using the resist pattern as a mask to form contact holes in each of them.
Next, a sputtering process is used to form a transparent conductive film having a thickness of 100 nm made of an ITO (indium tin oxide) throughout the substrate. The transparent conductive film is then patterned into a predetermined shape, thereby forming pixel electrodes that are connected to the source electrodes through contact holes. At the same time, drain terminal top electrodes are formed which are connected to the drain terminal bottom electrodes through other contact holes, and gate electrodes top electrodes are formed which are connected to the gate electrode bottom electrodes through other contact holes.
As thus described, according to the disclosure of Patent Document 4, when gate terminals and drain terminals are formed, gate terminal bottom electrodes and drain terminal bottom electrodes are formed; a passivation film covering the gate terminal bottom electrodes and the drain terminal bottom electrodes is formed; the passivation film is etched to provide contact holes; and, at the same time when pixel electrodes are formed, gate terminal top electrodes constituted by transparent conductive films are formed in connection with the gate terminal bottom electrodes through contact holes, and drain terminal top electrodes constituted by transparent conductive films are formed in connection with the drain terminal bottom electrodes through contact holes.
Patent Document 5 discloses a liquid crystal display in which an overcoat layer (hereinafter referred to as “OC layer”) made of an insulating organic resin material is formed on an array substrate having switching elements formed thereon. A passivation film as described above is constituted by an organic insulating film such as a SiN film and is formed with a thickness in the range from 300 to 400 nm, in general. On the contrary, an OC layer is characterized in that it is formed with a thickness in the range from 1000 to 3000 nm which is very much greater than that of a passivation film. Further, an OC layer is characterized in that it is formed of a resin having a relatively small dielectric constant (about 3 or less). Because of the two features, a liquid crystal display formed with an OC layer is advantageous in that a parasitic capacity degrading TFT characteristics can be made small. A liquid crystal display formed with an OC layer is also advantageous in that manufacturing steps can be simple because contact holes are formed using the OC layer made of a photosensitive material as an etching mask.
FIGS. 16A and 16B show a configuration of a TFT substrate of a reflective liquid crystal display formed with an OC layer according to the related art. FIG. 16A shows a configuration of the neighborhood of electrode relaying regions of gate terminals of the TFT substrate taken in a direction perpendicular to the substrate surface, and FIG. 16B shows a section taken along the line X-X in FIG. 16A. As shown in FIGS. 16A and 16B, gate terminal bottom electrodes 130 formed of the same material as gate bus lines are formed on a glass substrate 106. In general, a gate terminal bottom electrode 130 has a multi-layer structure which frequently comprises an aluminum (Al) type metal layer 130a having a relatively low resistance formed as a bottom layer and a high melting point metal layer 130b formed as a top layer. An insulation film 132 is formed on the gate terminal bottom electrodes 130. A protective film 134 is formed on the insulation film 132. An OC layer 136 is formed on the protective film 134. For example, the surface of the OC layer 136 is formed with irregularities or wrinkles.
Openings are formed in the OC layer 136, the protective film 134 and the insulation film 132 above the gate terminal bottom electrodes 130 to form electrode relaying regions 138. Gate terminal top electrodes 140 made of the same material as that of pixel electrodes (reflective electrodes) are formed on the OC layer 136. For example, agate terminal top electrode 140 has a multi-layer structure comprising an ITO layer 140a, a silver (Ag) alloy layer 140b and an ITO layer 140a. The gate terminal top electrodes 140 are connected to the gate terminal bottom electrodes 130 in the electrode relaying regions 138.
FIGS. 17A and 17B show a configuration of a TFT substrate of a transmissive liquid crystal display having a CF-on-TFT structure according to the related art. FIG. 17A shows a configuration of the neighborhood of electrode relaying regions of gate terminals of the TFT substrate taken in a direction perpendicular to the substrate surface, and FIG. 17B shows a section taken along the line Z-Z in FIG. 17A. As shown in FIGS. 17A and 17B, gate terminal bottom electrodes 130 made of the same material as that of gate bus lines are formed on a glass substrate 106. An insulation film 132 is formed on the gate terminal bottom electrodes 130. A protective film 134 is formed on the insulation film 132. Resin CF layers 144 in any of red (R), green (G) and blue (B) are formed on the protective film 134. An OC layer 136 is formed on the resin CF layers 144.
Openings are formed in the OC layer 136, the resin CF layers 144, the protective film 134 and the insulation film 132 above the gate terminal bottom electrodes 130 to form electrode relaying regions 138. Gate terminal top electrodes 140 made of the same material as that of pixel electrodes (e.g., an ITO) are formed on the resin CF layers 144. The gate terminal top electrodes 140 are connected to the gate terminal bottom electrodes 130 in the electrode relaying regions 138.
Incidentally, the documents of the related art are as follows:
Patent Document 1: Japanese Patent Laid-Open No. JP-A-2001-324725
Patent Document 2: Japanese Patent Laid-Open No. JP-A-2001-53283
Patent Document 3: Japanese Patent Laid-Open No. JP-A-11-281993
Patent Document 4: Japanese Patent Laid-Open No. JP-A-6-202153
Patent Document 5: Japanese Patent Laid-Open No. JP-A-2000-231123
However, resin layers such as the OC layer 136 and the resin CF layers 144 are poorer than a passivation film in adhesion to the gate terminal top electrodes 140 that are formed on the resin layers from an electrode material such as an ITO. A problem can therefore arise in that the gate terminal top electrodes 140 formed directly on the OC layer 136 or resin CF layers 144 are flaked to cause conduction failures and shorting between adjoining terminals. Another problem arises in that the patterning of the gate terminal top electrodes 140 is apt to leave residues of the electrode material that can cause shorting between adjoining terminals and to result in etching defects such as a small pattern width which can cause an increase in resistance.
Liquid crystal displays are manufactured through a TFT array fabrication step, a CF fabrication step, a panel fabrication step and a unit fabrication step. At the unit fabrication step, driver ICs are mounted to gate terminals and drain terminals on a TAB (tape automated bonding) basis. A liquid crystal display having a connection defect attributable to misalignment of a driver IC during mounting is repaired by peeling the TAB terminal and reapplying the terminal thereafter. In the above-described configuration, since a top electrode is peeled along with the OC layer 136 or resin CF layer 144 when the TAB terminal is peeled, a problem arises in that it is difficult to repair.
FIGS. 18A, 18B, 19A and 19B show configurations of a TFT substrate in which the above-described problems are solved. FIGS. 18A and 18B show a configuration of a TFT substrate of a reflective liquid crystal display formed with an OC layer. FIG. 18A shows a configuration of the neighborhood of electrode relaying regions of gate terminals of the TFT substrate taken in a direction perpendicular to the substrate surface, and FIG. 18B shows a section taken along the line Y-Y in FIG. 18A. As shown in FIGS. 18A and 18B, an OC layer 136, a protective film 134 and an insulation film 132 between the adjoining gate terminals have end faces that are substantially aligned with an end face of gate terminal bottom electrodes 130 located on the side of electrode relaying regions 138. Protrusions 142 are formed on the end faces of the OC layer 136, the protective film 134 and the insulation film 132 substantially in the middle of the intervals between the adjoining gate terminals such that they protrude toward an end of the substrate (leftward in FIG. 18A), the protrusions being formed like triangles whose sections in parallel with the substrate surface have an acute apical angle. The protrusions 142 are provided to prevent the adjoining gate terminals from being shorted by etching residues that are left when gate terminal top electrodes 140 are patterned.
FIGS. 19A and 19B show a configuration of a TFT substrate of a transmissive liquid crystal display having a CF-on-TFT structure. FIG. 19A shows a configuration of the neighborhood of electrode relaying regions of the TFT substrate taken in a direction perpendicular to the substrate surface, and FIG. 19B shows a section taken along the line W-W in FIG. 19A. As shown in FIGS. 19A and 19B, an OC layer 136, a resin CF layer 144, a protective film 134 and an insulation film 132 between the adjoining gate terminals have end faces that are shifted toward a display area (rightward in FIGS. 19A and 19B) from end faces of gate terminal top electrodes 140 located in electrode relaying regions 138. That is, the surface of the glass substrate 106 is exposed in regions between the adjoining gate terminals on the substrate-end side (left-hand side in FIGS. 19A and 19B) of the end faces of the OC layer 136, the resin CF layer 144, the protective film 134 and the insulation film 132. Protrusions 142 are formed on the end faces of the OC layer 136, the protective film 134 and the insulation film 132 substantially in the middle of the intervals between the adjoining gate terminals such that they protrude toward the end of the substrate, the protrusions being formed like triangles whose sections in parallel with the substrate surface have an acute apical angle. The protrusions 142 are provided to prevent the adjoining gate terminals from being shorted by etching residues that are left when gate terminal top electrodes 140 are patterned.
On the TFT substrates shown in FIGS. 18A to 19B, the OC layer 136 is removed to form the gate terminal top electrodes 140 in direct contact with the glass substrate 106, thereby preventing flaking of the gate terminal top electrodes 140. In the above-described configurations, however, since the end faces of the gate terminal bottom electrodes 130 located at the electrode relaying regions 138 are shaped steeply relative to the substrate surface, the gate terminal top electrodes 140 may be broken at steps formed on the end faces, which results in the problem of an increase in the resistance of the gate terminals. Further, corrosion is likely to occur at the end faces of the gate terminal bottom electrodes 130 located at the electrode relaying regions 138 because the underlying Al type metal layers 130a and the gate terminal top electrodes 140 made of an ITO are in contact with each other, which results in a problem in that line breakage can occur. Thus, sufficient consideration must be paid for breakage of the gate terminal top electrodes 140 and electrical connection between the gate terminal top electrodes 140 and the gate terminal bottom electrodes 130 in the electrode relaying regions 138.